Level-shifters are typically deployed at locations where signals transition from a low voltage power supply domain to a high voltage power supply domain. FIG. 1 is a conventional cross-coupled level-shifter 100 with cross-coupled P-transistors MP1 and MP2 connected to pull-down N-transistors MN1 and MN2 respectively. The high voltage power supply domain VCCH connects to the P-transistors MP1 and MP2 while the signals (IN and INBL) generated in the low voltage power supply domain VCCL control the gates of the pull-down N-transistors MN1 and MN2, where INBL is generated by an inverter INV1 operating on VCCL power supply. The signal OUT is the level-shifted signal, i.e. the signal OUT (unlike IN signal) has a logical high level nearly equal to VCCH power supply level. The signal OUT can be driven by another inverter INV2 that generates OUTB, where INV2 operates on the VCCH power supply level.
Level-shifters, such as level-shifter 100, add to the overall power dissipation of the processor that comprises the level-shifter 100. The power dissipation increases as the voltage difference between VCCH and VCCL power supply levels increase. The level-shifter 100 is designed for a certain small range of process, temperature, and voltage (PVT), i.e. for specific VCCL and VCCH power supply levels to generate an OUT signal with specific duty cycle and rise/fall signal slopes, and with specific propagation delay.
As signal speed (e.g., frequency of signal IN) increases and the available power supply voltage level, i.e. VCCL, decreases (e.g., decreasing from 1.2V to 0.7V and lower), the conventional cross-coupled level-shifter 100 begins to suffer from duty cycle degradation, higher propagation delay, and non-uniform rise and fall slopes of the signal OUT. A non-50% duty cycle of the OUT signal may reduce timing margins at clock domain crossings as the OUT signal propagates through various clock domains.
Generally, to optimize the level-shifter 100 for a certain PVT, and for specific VCCL and VCCH power supply levels to generate an OUT signal with a certain duty cycle and rise/fall signal slopes, and with certain propagation delay, the size (W/L) of the P-transistors MP1 and MP2 are selected to balance the cross-coupling operation of the P-transistor latch (MP1 and MP2) and the pull-down strength of the N-transistors MN1 and MN2. However, for a certain range of PVT conditions and large difference between power supply voltage levels VCCH and VCCL, the latch of the level-shifter 100 exhibits meta-stability resulting in increased propagation delay and non-50% duty cycle at the signal OUT.